The present invention relates to a multi-processor system and a method for synchronizing among a plurality of processors, and more particularly to a multi-processor system and a method for synchronizing among a plurality of processors with a simplified cache protocol.
In a multi-processor system, when either the same data or adjacent data are repeatedly accessed, the access to a main memory is reduced by using data held in a cache memory. Thus, the limited bandwidth outside the processor is effectively utilized.
In a multi-processor system, when data of the same memory area is held in cache memories of different processors, if the data is updated by one processor of the multi-processor system, then the data should be updated in the cache memories of other processors of the multi-processor system to be consistent with the corresponding data in the other processors. If the data is not updated, a "cache consistency problem" occurs. In this case, all of the corresponding data in the system are updated. Otherwise, all of the corresponding data in the cache memories of the other processors will be invalid before updating. These protocols to maintain consistency with other cache memories are called "cache consistency protocols".
Even when any one of the above-described protocols is employed, either the update request or the invalidation request should be issued for a plurality of corresponding data which are physically separated from each other. This protocol is realized by issuing the request to all of the processors or specific processors. The specific processors are selected according to a table storing correspondence data between cache memories associated with the specific processors and data.
For example, if a variable "X" is shared by a processing unit #1 and a processing unit #2, then a cache memory state of the entry having the variable "X" is referred to as a "shared" state. At this time, when the variable "X" is written in the processing unit #1, the state of the corresponding entry of the processing unit #2 becomes an "invalid" state, and then the state of this entry of the processing unit #1 becomes an "update" state. With this operation, it is assured that the incorrect data is not read in the processing unit #2, and furthermore it is assured that the correct (e.g., most recent) value of the variable "X" is located in the cache memory of the processing unit #1. Then, when the variable "X" is subsequently read by the processing unit #2, after the entry of the cache memory of the processing unit #1 is again written into the shared memory, this entry is transferred to the cache memory of the processing unit #2, and then the state of the entries of both the processing units #1 and #2 becomes the "shared" state.
Such an operation is required so as to assure the data consistency in every entry. However, this conventional multi-processor system has a problem in that a total number of request transfer operations for the updating operation and the invalidation operation is increased. In particular, a serious problem may be caused when the respective processors are connected by the network.
A second problem is that, since a plurality of variables are usually included in a single entry, when a variable is updated, other variables are adversely affected. For example, the variable "Y" is included in the same entry as the above-described variable "X", when the variable "Y" is updated by the processing unit #1 under a "shared" state, the entry of the processing unit #2 is invalidated. Accordingly, the data of the variable "X" would also be deleted from the cache memory.
On the other hand, in parallel processing operations, if processing units are synchronized, then assuring cache states in real-time is not necessarily required.